Perspectives d'utilisation des modèles électriques des éléments à faibles dimensions pour le calcul schémotechnique des grands circuits intégrés bipolairesPETROSYANTS, K. O.Mikroèlektronika (Moskva). 1983, Vol 12, Num 5, pp 440-451, issn 0544-1269Article

Evaluation de la longueur moyenne et de la capacité traçante des liaisons des grands circuits intégrés matriciels des calculateursPAJZULAEV, B. N.Mikroèlektronika (Moskva). 1983, Vol 12, Num 5, pp 457-463, issn 0544-1269Article

Liquid crystal dysplay panels and LCD driver LS'sTACHI, S; SATO, E; KINUGAWA, K et al.Hitachi review. 1984, Vol 33, Num 5, pp 255-260, issn 0018-277XArticle

High-speed digital LSIsISHIKAWA, H.Fujitsu scientific and technical journal. 1986, Vol 22, Num 2, pp 93-97, issn 0016-2523Article

Custom-designed integrated circuits for data modemsBROWNLIE, J. D; JACKETS, A. E; GUNBY, D. M et al.British Telecom technology journal. 1985, Vol 3, Num 1, pp 14-19, issn 0265-0193Article

43-ps 5.2-GHz macrocell array LSI'sSUZUKI, M; HIRATA, M; KONAKA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1182-1188, issn 0018-9200Article

All-electronic telephone set with one chip LSI, realizing various telephone set stylesKATO, K; KAWASHIMA, I.Japan Telecommunications Review. 1984, Vol 26, Num 1, pp 13-18, issn 0021-4744Article

Symmetric displacement algorithms for the timing analysis of large scale circuitsDE MICHELI, G; NEWTON, A. R; SANGIOVANNI-VINCENTELLI, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1983, Vol 2, Num 3, pp 167-180, issn 0278-0070Article

High-density packaging of main storageTAKAMURA, M; IKEHARA, S.Fujitsu scientific and technical journal. 1985, Vol 21, Num 4, pp 452-460, issn 0016-2523Article

A class of odd-weight-column SEC-DED-SbED codes for memory system applicationsKANEDA, S.IEEE transactions on computers. 1984, Vol 33, Num 8, pp 737-739, issn 0018-9340Article

A new global router for gate array LSITSUKIYAMA, S; HARADA, I; FUKUI, M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1983, Vol CAD.2, Num 4, pp 313-321, issn 0278-0070Article

Quality assurance system and reliability testing of LSI circuitsWURNIK, F. M.Microelectronics and reliability. 1983, Vol 23, Num 4, pp 709-715, issn 0026-2714Article

Calibration-free parallel optical-interconnection subsystem implemented by a GByte/s-array optical transceiver and a one-chip link LSIsYOSHIKAWA, T; MATSUOKA, H.SPIE proceedings series. 1998, pp 524-527, isbn 0-8194-2949-XConference Paper

H series microcomputer familyINAYOSHI, H; NISHIMUKAI, T; MAEJIMA, H et al.Hitachi review. 1987, Vol 36, Num 5, pp 269-274, issn 0018-277XArticle

RNS digital filtering structures for wafer-scale integrationLAMACCHIA, B. W; REDINBO, G. R.IEEE journal on selected areas in communications. 1986, Vol 4, Num 1, pp 67-80, issn 0733-8716Article

Incremental processing applied to Munkres' algorithm and its application in Steinberg's placement procedureCARTER, H. W; BREUER, M. A; SYED, Z. A et al.SIAM journal on algebraic and discrete methods. 1985, Vol 6, Num 2, pp 210-219, issn 0196-5212Article

Approche multicritère pour le choix des liaisons optimales dans un grand circuit intégréBATALOV, B. V; LYASNIKOV, E. P; SHCHEMELININ, V. M et al.Mikroèlektronika (Moskva). 1984, Vol 13, Num 1, pp 3-14, issn 0544-1269Article

An integrated approach to statistical modeling of bipolar devices for LSIFOX, P. E.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 765-772, issn 0018-9200Article

Hemispherical retarding type energy analyzer for LSI testing by an electron beamITO, A; GOTO, Y; FURUKAWA, Y et al.Fujitsu scientific and technical journal. 1983, Vol 19, Num 4, pp 431-441, issn 0016-2523Article

A new diagnostic test for operating margin problems in LSI memoryHAMAGUCHI, S; ISHIKAWA, K.IEEE journal of solid-state circuits. 1983, Vol 18, Num 4, pp 409-413, issn 0018-9200Article

Advanced C²MOS speech synthesizersSUZUKI, Y; TANAKA, F; SHIGEHARA, H et al.Microprocessors and microsystems. 1983, Vol 7, Num 10, pp 469-474, issn 0141-9331Article

RELAX: a new circuit simulator for large scale MOS integrated circuitsLELARASMEE, E; SANGIOVANNI-VINCENTELLI, A.Computer-aided design. 1983, Vol 15, Num 5, pp 262-270, issn 0010-4485Article

Directions du développement de l'assurance mathématique pour l'analyse automatisée d'un grand circuit intégréNORENKOV, I. P.Mikroèlektronika (Moskva). 1984, Vol 13, Num 3, pp 222-227, issn 0544-1269Article

Delay-time modeling for ED MOS logic LSITOKUDA, T; OKAZAKI, K; SAKASHITA, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1983, Vol 2, Num 3, pp 129-134, issn 0278-0070Article

Memory LSI soft errors and countermeasures in computersSAKAMOTO, F; NAKAMURA, T; MASUMOTO, K et al.NEC research & development. 1989, Num 92, pp 142-150, issn 0547-051X, 9 p.Article